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W9812G2IB 1m 4 banks 32bits sdram publication release date: mar. 09, 2010 - 1 - revision a04 table of contents- 1. general des cription ............................................................................................................ .. 3 2. features....................................................................................................................... ............... 3 3. available par t number .......................................................................................................... 3 4. ball config uration............................................................................................................. .... 4 5. ball descri ption ............................................................................................................... ....... 5 6. block diagram.................................................................................................................. ......... 6 7. functional desc ription ........................................................................................................ 7 7.1 power up and in itialization ................................................................................................. 7 7.2 programming m ode regist er .............................................................................................. 7 7.3 bank activate command .................................................................................................... 7 7.4 read and write a ccess modes .......................................................................................... 7 7.5 burst read command ........................................................................................................ 8 7.6 burst write command......................................................................................................... 8 7.7 read interrupt ed by a read ............................................................................................... 8 7.8 read interrupt ed by a write................................................................................................ 8 7.9 write interrupted by a write ................................................................................................ 8 7.10 write interrupted by a read................................................................................................ 8 7.11 burst stop command.......................................................................................................... 9 7.12 addressing sequence of sequentia l mode......................................................................... 9 7.13 addressing sequence of interleave mode.......................................................................... 9 7.14 auto-prechar ge command................................................................................................ 10 7.15 precharge command........................................................................................................ 10 7.16 self refres h comm and..................................................................................................... 10 7.17 power down mode ............................................................................................................ 11 7.18 no operatio n command ................................................................................................... 11 7.19 deselect command .......................................................................................................... 11 7.20 clock suspend mode........................................................................................................ 11 8. operatio n mode................................................................................................................. ..... 12 8.1 simplified stat ed diagra m ................................................................................................ 13 9. electrical chara cteristics ............................................................................................. 14 9.1 absolute maximu m ratings .............................................................................................. 14 9.2 recommended dc operat ing condit ions ........................................................................ 14 9.3 capacitance .................................................................................................................... .. 15 www.datasheet.co.kr datasheet pdf - http://www..net/
W9812G2IB publication release date: mar. 09, 2010 - 2 - revision a04 9.4 dc characteri stics ............................................................................................................ 1 5 9.5 ac characteristics and operating co ndition .................................................................... 16 10. timing wa veforms............................................................................................................... ... 18 10.1 command input timing ..................................................................................................... 18 10.2 read ti ming.................................................................................................................... .. 19 10.3 control timing of input/output data ................................................................................. 20 10.4 mode register set cycle .................................................................................................. 21 11. operating timi ng example .................................................................................................. 22 11.1 interleaved bank read (burst length = 4, cas latency = 3) .......................................... 22 11.2 interleaved bank read (burst length = 4, cas latency = 3, auto-precharge) ............... 23 11.3 interleaved bank read (burst length = 8, cas latency = 3) .......................................... 24 11.4 interleaved bank read (burst length = 8, cas latency = 3, auto-precharge) ............... 25 11.5 interleaved bank write (burst lengt h = 8) ....................................................................... 26 11.6 interleaved bank write (burst length = 8, auto -precharge) ............................................ 27 11.7 page mode read (burst lengt h = 4, cas lat ency = 3)................................................... 28 11.8 page mode read / write (burst length = 8, cas latency = 3) ....................................... 29 11.9 auto-precharge read (burst length = 4, cas latency = 3) ............................................ 30 11.10 auto-precharge write (burst lengt h = 4).......................................................................... 31 11.11 auto refres h cycle ........................................................................................................... 32 11.12 self refres h cycle ............................................................................................................ 3 3 11.13 burst read and single write (burst length = 4, cas latency = 3) ................................. 34 11.14 power down mode ............................................................................................................ 35 11.15 auto-precharge timi ng (read cy cle) ............................................................................... 36 11.16 auto-precharge timing (write cy cle) ............................................................................... 37 11.17 timing chart of read to write cycle ................................................................................ 38 11.18 timing chart of write to read cycle ................................................................................ 38 11.19 timing chart of burst stop cy cle (burst st op comma nd) ............................................... 39 11.20 timing chart of burst stop cy cle (precharge command)................................................ 39 11.21 cke/dqm input timing (write cycle) .............................................................................. 40 11.22 cke/dqm input timi ng (read cy cle) .............................................................................. 41 12. package specific ation......................................................................................................... 4 2 12.1 tfbga 90 balls (8x13 mm 2 , ball pitch: 0.8 mm, ?=0.45mm) .......................................... 42 13. revision histor y............................................................................................................... ...... 43 www.datasheet.co.kr datasheet pdf - http://www..net/
W9812G2IB publication release date: mar. 09, 2010 - 3 - revision a04 1. general description W9812G2IB is a high-speed synchronous dynamic random access memory (sdram), organized as 1,048,576 words 4 banks 32 bits. W9812G2IB delivers a data bandwidth of up to 166m words per second (-6). for different application, W9812G2IB is sorted into following speed grades:-6/-6i/-6a and -75. the -6/-6i/-6a is compliant to the 166mhz/c l3 specification (the -6i industrial grade and -6a automotive grade which is guaranteed to support -40c ~ 85c). the -75 is compliant to the 133mhz/cl3 specification. accesses to the sdram are burst oriented. consecutive memory location in one page can be accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an active command. column addresses are automatically gener ated by the sdram internal counter in burst operation. random column read is also possible by providing its address at each clock cycle. the multiple bank nature enables interleaving amon g internal banks to hide the precharging time. by having a programmable mode r egister, the system can change burst length, latency cycle, interleave or sequential burst to maximize its performance. W9812G2IB is ideal for main memory in high performance applications. 2. features ? 2.7v~3.6v power supply ? up to 166 mhz clock frequency ? 1,048,576 words 4 banks 32 bits organization ? self refresh mode ? cas latency: 2 and 3 ? burst length: 1, 2, 4, 8 and full page ? burst read, single writes mode ? byte data controlled by dqm0-3 ? auto-precharge and controlled precharge ? 4k refresh cycles / 64 ms ? interface: lvttl ? packaged in tfbga 90 ball (8x13 mm 2 ), using lead free materials with rohs compliant 3. available part number part number speed maximum self refresh current operating temperature W9812G2IB-6 166mhz/cl3 2ma 0 c ~ 70 c W9812G2IB-6i 166mhz/cl3 2ma -40 c ~ 85 c W9812G2IB-6a 166mhz/cl3 2ma -40 c ~ 85 c W9812G2IB-75 133mhz/cl3 2ma 0 c ~ 70 c www.datasheet.co.kr datasheet pdf - http://www..net/
W9812G2IB publication release date: mar. 09, 2010 - 4 - revision a04 4. ball configuration cke a8 a6 dq23 a4 clk a9 a7 a5 we# cas# cs# bs0 a10 a1 a3 dqm0 ras# bs1 a0 a2 1 26 5 7 9 8 4 3 c b a p n g d e m h l f k r j vdd vdd vdd vddq vddq vddq vddq vddq vdd vddq vddq vddq vddq vssq vssq vssq vssq vssq vssq vssq vssq vssq vssq vddq nc nc a11 nc nc dqm2 dq21 dq19 dq20 dq22 dq18 dq17 dq16 dq7 dq6 dq5 dq1 dq3 dq4 dq0 dq2 vss vss vss vss dqm3 dqm1 dq26 dq24 dq28 dq27 dq25 dq29 dq30 dq31 dq15 dq13 dq11 dq12 dq14 dq10 dq9 dq8 nc nc top view www.datasheet.co.kr datasheet pdf - http://www..net/
W9812G2IB publication release date: mar. 09, 2010 - 5 - revision a04 5. ball description ball number symbol function description g8,g9,f7,f3,g1,g2, g3,h1,h2,j3,g7,h9 a0 ? a11 address multiplexed pins for row and column address. row address: a0 ? a11. column address: a0 ? a7. a10 is sampled during a precharge command to determine if all banks are to be precharged or bank selected by bs0, bs1. j7,h8 bs0, bs1 bank select select bank to activate during row address latch time, or bank to read/write during address latch time. r8,n7,r9,n8,p9,m8, m7,l8,l2,m3,m2,p1, n2,r1,n3,r2,e8,d7, d8,b9,c8,a9,c7,a8, a2,c3,a1,c2,b1,d2, d3,e2 dq0 ? dq31 data input/ output multiplexed pins for data output and input. j8 cs chip select disable or enable the command decoder. when command decoder is disabled, new command is ignored and previous operation continues. j9 ras row address strobe command input. when sampled at the rising edge of the clock ras , cas and we define the operation to be executed. k7 cas column address strobe referred to ras k8 we write enable referred to ras k9,k1,f8,f2 dqm0~3 input/output mask the output buffer is placed at hi-z (with latency of 2) when dqm is sampled high in read cycle. in write cycle, sampling dqm high will block the write operation with zero latency. j1 clk clock inputs system clock used to sample inputs on the rising edge of clock. j2 cke clock enable cke controls the clock activation and deactivation. when cke is low, power down mode, suspend mode, or self refresh mode is entered. a7,f9,l7,r7 vdd power power for input buffers and logic circuit inside dram. a3,f1,l3,r3 vss ground ground for input buffers and logic circuit inside dram. b2,b7,c9,d9,e1,l1, m9,n9,p2,p7 vddq power for i/o buffer separated power from vdd, to improve dq noise immunity. b8,b3,c1,d1,e9,l9, m1,n1,p3,p8 vssq ground for i/o buffer separated ground from vss, to improve dq noise immunity. e3,e7,h3,h7,k2,k3 nc no connection no connection www.datasheet.co.kr datasheet pdf - http://www..net/
W9812G2IB publication release date: mar. 09, 2010 - 6 - revision a04 6. block diagram dq0 dq31 dqmn clk cke cs ras cas we a10 a0 a9 a11 bs0 bs1 . clock buffer command decoder address buffer refresh counter column counter control signal generator mode register and emrs column decoder sense amplifier cell array bank #2 column decoder sense amplifier cell array bank #0 column decoder sense amplifier cell array bank #3 data control circuit dq buffer column decoder sense amplifier cell array bank #1 note: the cell array configuration is 4096 * 256 * 32 dmn row decoder row decoder row decoder row decoder www.datasheet.co.kr datasheet pdf - http://www..net/
W9812G2IB publication release date: mar. 09, 2010 - 7 - revision a04 7. functional description 7.1 power up and initialization the default power up state of the mode register is unspecified. the following power up and initialization sequence need to be followed to guaran tee the device being preconditioned to each user specific needs. during power up, all v dd and v ddq pins must be ramp up simultaneously to the specified voltage when the input signals are held in the ?nop? st ate. the power up voltage must not exceed v dd +0.3v on any of the input pins or v dd supplies. after power up, an initial pause of 200 s is required followed by a precharge of all banks usin g the precharge command. to prevent data contention on the dq bus during power up, it is required that the dqm and cke pins be held high during the initial pause period. once all banks have been precharged, the mode register set command must be issued to initialize the mode register. an additional eight auto refresh cycles (cbr) are also required before or after programming the mode register to ensure proper subsequent operation. 7.2 programming mode register after initial power up, the mode register set command must be issued for proper device operation. all banks must be in a precharged state and cke must be high at least one cycle before the mode register set command can be issued. the mode register set command is activated by the low signals of ras , cas , cs and we at the positive edge of the clock. the address input data during this cycle defines the parameters to be set as shown in the mode register operation table. a new command may be issued following the mode register set command once a delay equal to t rsc has elapsed. please refer to the next page for mo de register set cycle and operation table. 7.3 bank activate command the bank activate command must be applied before any read or write operation can be executed. the operation is similar to ras activate in edo dram. the delay from when the bank activate command is applied to when the first read or write operation can begin must not be less than the ras to cas delay time (t rcd ). once a bank has been activated it must be precharged before another bank activate command can be issued to the same bank. the minimum time interval between successive bank activate commands to the same bank is det ermined by the ras cycle time of the device (t rc ). the minimum time interval between interleaved bank activate commands (bank a to bank b and vice versa) is the bank to bank delay time (t rrd ). the maximum time that each bank can be held active is specified as t ras (max). 7.4 read and write access modes after a bank has been activated, a read or write cy cle can be followed. this is accomplished by setting ras high and cas low at the clock rising edge after minimum of t rcd delay. we pin voltage level defines whether the access cycle is a read operation ( we high), or a write operation ( we low). the address inputs determine the starting column address. reading or writing to a different row within an activated bank requires the bank be precharged and a new bank activate command be issued. when more than one bank is activated, interleaved bank read or write operations are possible. by using the programmed burst length and alternating the access and precharge operations between multiple banks, seamless data access operation among www.datasheet.co.kr datasheet pdf - http://www..net/
W9812G2IB publication release date: mar. 09, 2010 - 8 - revision a04 many different pages can be realized. read or write commands can also be issued to the same bank or between active banks on every clock cycle. 7.5 burst read command the burst read command is initiated by applying logic low level to cs and cas while holding ras and we high at the rising edge of the clock. the address inputs determine the starting column address for the burst. the mode register sets type of burst (sequential or interleave) and the burst length (1, 2, 4, 8 and full page) during the mode register set up cycle. table 2 and 3 in the next page explain the address sequence of in terleave mode and sequential mode. 7.6 burst write command the burst write command is initiated by applying logic low level to cs , cas and we while holding ras high at the rising edge of t he clock. the address inputs determine the starting column address. data for the first burst write cycle must be applied on the dq pins on the same clock cycle that the write command is issued. the remaining data inputs must be supplied on each subsequent rising clock edge until the burst length is completed. data supplied to the dq pins after burst finishes will be ignored. 7.7 read interrupted by a read a burst read may be interrupted by another read co mmand. when the previous burst is interrupted, the remaining addresses are overrid den by the new read address with the full burst length. the data from the first read command continues to appear on the outputs until the cas latency from the interrupting read command the is satisfied. 7.8 read interrupted by a write to interrupt a burst read with a write comm and, dqm may be needed to place the dqs (output drivers) in a high impedance state to avoid dat a contention on the dq bus. if a read command will issue data on the first and second clocks cycles of the write operation, dqm is needed to insure the dqs are tri-stated. after that point the write command will have control of the dq bus and dqm masking is no longer needed. 7.9 write interrupted by a write a burst write may be interrupted before completion of the burst by another write command. when the previous burst is interrupted, the remaining ad dresses are overridden by the new address and data will be written into the device until the programmed burst length is satisfied. 7.10 write interrupted by a read a read command will interrupt a burst write operat ion on the same clock cycle that the read command is activated. the dqs must be in the hi gh impedance state at least one cycle before the new read data appears on the outputs to avoid data contention. when the read command is activated, any residual data from t he burst write cycl e will be ignored. www.datasheet.co.kr datasheet pdf - http://www..net/
W9812G2IB publication release date: mar. 09, 2010 - 9 - revision a04 7.11 burst stop command a burst stop command may be used to terminate the existing burst operation but leave the bank open for future read or write commands to the same page of the active bank, if the burst length is full page. use of the burst stop command during other burst length operations is illegal. the burst stop command is defined by having ras and cas high with cs and we low at the rising edge of the clock. the data dqs go to a high impedance stat e after a delay which is equal to the cas latency in a burst read cycle interrupted by burst stop. 7.12 addressing sequence of sequential mode a column access is performed by increasing the addr ess from the column address which is input to the device. the disturb address is varied by the burst length as shown in table 2. table 2 address sequence of sequential mode data access address burst length data 0 n bl = 2 (disturb address is a0) data 1 n + 1 no address carry from a0 to a1 data 2 n + 2 bl = 4 (disturb addresses are a0 and a1) data 3 n + 3 no address carry from a1 to a2 data 4 n + 4 data 5 n + 5 bl = 8 (disturb addresses are a0, a1 and a2) data 6 n + 6 no address carry from a2 to a3 data 7 n + 7 7.13 addressing sequence of interleave mode a column access is started in the input column address and is performed by inverting the address bit in the sequence shown in table 3. table 3 address sequence of interleave mode data access address burst length data 0 a8 a7 a6 a5 a4 a3 a2 a1 a0 bl = 2 data 1 a8 a7 a6 a5 a4 a3 a2 a1 a0 data 2 a8 a7 a6 a5 a4 a3 a2 a1 a0 bl = 4 data 3 a8 a7 a6 a5 a4 a3 a2 a1 a0 data 4 a8 a7 a6 a5 a4 a3 a2 a1 a0 bl = 8 data 5 a8 a7 a6 a5 a4 a3 a2 a1 a0 data 6 a8 a7 a6 a5 a4 a3 a2 a1 a0 data 7 a8 a7 a6 a5 a4 a3 a2 a1 a0 www.datasheet.co.kr datasheet pdf - http://www..net/
W9812G2IB publication release date: mar. 09, 2010 - 10 - revision a04 7.14 auto-precharge command if a10 is set to high when the read or write command is issued, then the auto-precharge function is entered. during auto-prechar ge, a read command will execute as nor mal with the exception that the active bank will begin to precharge automatically before all burst read cycles have been completed. regardless of burst length, it will begin a certain nu mber of clocks prior to the end of the scheduled burst cycle. the number of clocks is determined by cas latency. a read or write command with auto-precharge c an not be interrupted before the entire burst operation is completed. therefore, use of a read, write or precharge command is prohibited during a read or write cycle with auto-precharge. once t he precharge operation has st arted, the bank cannot be reactivated until the precharge time (t rp ) has been satisfied. issue of auto-precharge command is illegal if the burst is set to full page length. if a 10 is high when a write command is issued, the write with auto-precharge function is initiated. the sdram automatically enters the precharge operation two clocks delay from the last burst write cycle. this delay is referred to as write t wr . the bank undergoing auto-precharge can not be reactivated until t wr and t rp are satisfied. this is referred to as t dal , data-in to active delay (t dal = t wr + t rp ). when using the auto-precharge command, the interval between the bank activate command and the beginni ng of the internal precharge operation must satisfy t ras (min). 7.15 precharge command the precharge command is used to precharge or close a bank that has been activated. the precharge command is entered when cs , ras and we are low and cas is high at the rising edge of the clock. the precharge command can be used to precharge each bank separately or all banks simultaneously. three address bits, a10, bs0, and bs1, are used to define which bank(s) is to be precharged when the command is issued. after the precharge command is issued, the precharged bank must be reactivated before a new read or wr ite access can be executed. the delay between the precharge command and the activate command must be greater than or equal to the precharge time (t rp ). 7.16 self refresh command the self refresh command is defined by having cs , ras , cas and cke held low with we high at the rising edge of the clock. all banks must be idle prior to issuing the self refresh command. once the command is registered, cke must be held low to keep the device in self refresh mode. when the sdram has entered self refresh mode all of the external control si gnals, except cke, are disabled. the clock is internally disabled during self refresh operation to save power. the device will exit self refresh operation after cke is retur ned high. any subsequent commands can be issued after t xsr from the end of self refresh command. if, during normal operation, auto refresh cycles are issued in bursts (as opposed to being evenly distributed), a burst of 4,096 auto refresh cycles should be completed just prior to entering and just after exiting the self refresh mode. www.datasheet.co.kr datasheet pdf - http://www..net/
W9812G2IB publication release date: mar. 09, 2010 - 11 - revision a04 7.17 power down mode the power down mode is initiated by holding cke lo w. all of the receiver circuits except cke are gated off to reduce the power. the power down mode does not perform any refresh operations, therefore the device can not remain in power down mode longer than the refresh period (t ref ) of the device. the power down mode is exited by bringing ck e high. when cke goes high, a no operation command is required on the next rising clock edge, depending on t ck . the input buffers need to be enabled with cke held high for a period equal to t cks (min) + t ck (min). 7.18 no operation command the no operation command should be used in cases w hen the sdram is in a idle or a wait state to prevent the sdram from registering any unwanted commands between operations. a no operation command is registered when cs is low with ras , cas , and we held high at the rising edge of the clock. a no operation command will not terminate a previous operation that is still executing, such as a burst read or write cycle. 7.19 deselect command the deselect command performs the same function as a no operation command. deselect command occurs when cs is brought high, the ras , cas , and we signals become don?t cares. 7.20 clock suspend mode during normal access mode, cke must be held high enabling the clock. when cke is registered low while at least one of the banks is active, clock suspend mode is entered. the clock suspend mode deactivates the internal clock an d suspends any clocked operation t hat was currently being executed. there is a one clock delay between the registrati on of cke low and the time at which the sdram operation suspends. while in clock suspend mode, the sdram ignores any new commands that are issued. the clock suspend mode is exited by br inging cke high. there is a one clock cycle delay from when cke returns high to when clock suspend mode is exited. www.datasheet.co.kr datasheet pdf - http://www..net/
W9812G2IB publication release date: mar. 09, 2010 - 12 - revision a04 8. operation mode fully synchronous operations are performed to latc h the commands at the positive edges of clk. table 1 shows the truth table for the operation commands. table 1 truth table (note (1), (2)) command device state cken-1 cken dqm bs0, 1 a10 a0 ? a9 a11 cs ras cas we bank active idle h x x v v v l l h h bank precharge any h x x v l x l l h l precharge all any h x x x h x l l h l write active (3) h x x v l v l h l l write with auto-precharge active (3) h x x v h v l h l l read active (3) h x x v l v l h l h read with auto-precharge active (3) h x x v h v l h l h mode register set idle h x x v v v l l l l no ? operation any h x x x x x l h h h burst stop active (4) h x x x x x l h h l device deselect any h x x x x x h x x x auto - refresh idle h h x x x x l l l h self - refresh entry idle h l x x x x l l l h self refresh exit idle ( s.r. ) l l h h x x x x x x x x h l x h x h x x clock suspend mode entry active h l x x x x x x x x power down mode entry idle active (5) h h l l x x x x x x x x h l x h x h x x clock suspend mode exit acti ve l h x x x x x x x x power down mode exit any (power down) l l h h x x x x x x x x h l x h x h x x data write/output enable ac tive h x l x x x x x x x data write/output disable active h x h x x x x x x x notes: (1) v = valid x = don?t care l = low level h = high level (2) cken signal is input level when commands are provided. cken-1 signal is the input level one clock cycle before the command is issued. (3) these are state of bank designated by bs0, bs1 signals. (4) device state is full page burst operation. (5) power down mode can not be entered in the burst cycle. when this command asserts in the burst cycle, device state is clock suspend mode. www.datasheet.co.kr datasheet pdf - http://www..net/
W9812G2IB publication release date: mar. 09, 2010 - 13 - revision a04 8.1 simplified stated diagram mode register set idle cbr refresh self refresh row active power down precharge power on active power down write write suspend writea writea suspend read suspend read reada suspend reada precharge mrs ref act cke cke cke cke cke cke cke cke cke cke s e l f s e l f e x i t c k e c k e w r i t e w i t h read write a u t o p r e c h a r g e a u t o p r e c h a r g e r e a d w i t h write w r i t e r e a d p r e ( p r e c h a r g e t e r m i n a t i o n ) p r e ( p r e c h a r g e t e r m i n a t i o n ) read b s t b s t pre manual input automatic sequence mrs = mode register set ref = refresh act = active pre = precharge writea = write with auto-precharge reada = read with auto-precharge www.datasheet.co.kr datasheet pdf - http://www..net/
W9812G2IB publication release date: mar. 09, 2010 - 14 - revision a04 9. electrical characteristics 9.1 absolute maximum ratings parameter symbol rating unit notes input/output voltage v in , v out -0.5 ~ v dd + 0.5 (< 4.6v max.) v 1 power supply voltage v dd , v ddq -0.5 ~ 4.6 v 1 operating temperature(-6/-75) t opr 0 ~ 70 c 1 operating temperature(-6i/-6a) t opr -40 ~ 85 c 1 storage temperature t stg -55 ~ 150 c 1 soldering temperature (10s) t solder 260 c 1 power dissipation p d 1 w 1 short circuit output current i out 50 ma 1 note: 1. exposure to conditions beyond those listed under absolute ma ximum ratings may adversely affect the life and reliability of the device. 9.2 recommended dc operating conditions (t a = 0 to 70 c for -6/-75, t a = -40 to 85 c for -6i/-6a) parameter symbol min. typ. max. unit notes power supply voltage v dd 2.7 3.3 3.6 v i/o buffer supply voltage v ddq 2.7 3.3 3.6 v input high voltage v ih 2.0 - v dd + 0.3 v 1 input low voltage v il -0.3 - 0.8 v 2 output logic high voltage v oh 2.4 - - v i oh = -2ma output logic low voltage v ol - - 0.4 v i ol = 2ma input leakage current i i(l) -5 - 5 a 3 output leakage current i o(l) -5 - 5 a 4 notes: 1. v ih (max.) = v dd /v ddq +1.5v for pulse width < 5 ns. 2. v il (min.) = v ss /v ssq -1.5v for pulse width < 5 ns. 3. any input 0v < v in < v ddq. input leakage currents include hi-z output leakage for all bi-directional buffers with tri-state outputs. 4. output disabled, 0v v out v ddq. www.datasheet.co.kr datasheet pdf - http://www..net/
W9812G2IB publication release date: mar. 09, 2010 - 15 - revision a04 9.3 capacitance (v dd = 2.7v~3.6v, f = 1 mhz, t a = 25 c) parameter sym. min. max. unit input capacitance (a0 to a11, bs0, bs1, cs , ras , cas , we , dqm, cke) c i - 3.8 pf input capacitance (clk) c clk - 3.5 pf input/output capacitance c io - 6.5 pf note: these parameters are periodically sampled and not 100% tested 9.4 dc characteristics (v dd = 2.7v~3.6v, t a = 0 to 70 c for -6/-75, t a = -40 to 85 c for -6i/-6a) max. parameter sym. -6/-6i/-6a -75 unit notes operating current t ck = min., t rc = min. active precharge command cycling without burst operation 1 bank operation i dd1 130 110 3 standby current t ck = min, cs = v ih cke = v ih i dd2 45 35 3 v ih / l = v ih (min)/v il (max.) bank: inactive state cke = v il (power down mode) i dd2p 2 2 3 standby current clk = v il , cs = v ih cke = v ih i dd2s 15 15 v ih / l = v ih (min)/v il (max) bank: inactive state cke = v il (power down mode) i dd2ps 2 2 ma no operating current t ck = min., cs = v ih (min) cke = v ih i dd3 70 65 bank: active state (4 banks) cke = v il (power down mode) i dd3p 15 15 burst operating current t ck = min. read/ write command cycling i dd4 200 180 3, 4 auto refresh current t ck = min. auto refresh command cycling i dd5 230 210 3 self refresh current self refresh mode cke = 0.2v i dd6 2 2 www.datasheet.co.kr datasheet pdf - http://www..net/
W9812G2IB publication release date: mar. 09, 2010 - 16 - revision a04 9.5 ac characteristics and operating condition ( v dd = 2.7v~3.6v, t a = 0 to 70 c for -6/-75, t a = -40 to 85 c for -6i/-6a) (notes: 5, 6) -6/-6i/-6a -75 parameter sym. min. max. min. max. unit notes ref/active to ref/active command period t rc 60 65 active to precharge command period t ras 42 100000 45 100000 ns active to read/write command delay time t rcd 18 20 read/write(a) to read/write(b) command period t ccd 1 1 t ck precharge to active command period t rp 18 20 active(a) to active(b) command period t rrd 12 15 ns cl* = 2 2 2 write recovery time cl* = 3 t wr 2 2 t ck cl* = 2 10 1000 10 1000 clk cycle time cl* = 3 t ck 6 1000 7.5 1000 clk high level width t ch 2 2.5 8 clk low level width t cl 2 2.5 8 cl* = 2 6 6 access time from clk cl* = 3 t ac 5 5.4 9 cl* = 2 3 3 output data hold time cl* = 3 t oh 2 2 9 cl* = 2 6 6 output data high impedance time cl* = 3 t hz 5 5.4 7 output data low impedance time t lz 0 0 9 power down mode entry time t sb 0 6 0 7.5 transition time of clk (rise and fall) t t 1 1 data-in set-up time t ds 1.5 1.5 8 data-in hold time t dh 0.8 1.0 8 address set-up time t as 1.5 1.5 8 address hold time t ah 0.8 1.0 8 cke set-up time t cks 1.5 1.5 8 cke hold time t ckh 0.8 1.0 8 command set-up time t cms 1.5 1.5 8 command hold time t cmh 0.8 1.0 ns 8 refresh time t ref 64 64 ms mode register set cycle time t rsc 2 2 t ck exit self refresh to active command t xsr 72 75 ns *cl = cas latency www.datasheet.co.kr datasheet pdf - http://www..net/
W9812G2IB publication release date: mar. 09, 2010 - 17 - revision a04 notes: 1. operation exceeds ?a bsolute maximum ratings? may cause permanent damage to the devices. 2. all voltages are referenced to v ss 3. these parameters depend on the cycl e rate and listed values are measured at a cycle rate with the minimum values of t ck and t rc . 4. these parameters depend on the output loading conditions. specified values are obtained with output open. 5. power up sequence is further described in the ?functional description? section. 6. ac test load diagram . 50 ohms 1.4 v ac test load z = 50 ohms output 30pf 7. t hz defines the time at which the outputs achieve t he open circuit condition and is not referenced to output level. 8. assumed input transition time (t t ) = 1ns. if tr & tf is longer than 1ns, transie nt time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter ( the t t maximum can?t be more than 10ns for low frequency application.) 9. if clock rising time (t t ) is longer than 1ns, (t t /2-0.5)ns should be added to the parameter. www.datasheet.co.kr datasheet pdf - http://www..net/
W9812G2IB publication release date: mar. 09, 2010 - 18 - revision a04 10. timing waveforms 10.1 command input timing clk a0-a11 bs0,1 v ih v il tcmh t cms t ch t cl t t t t t cks t ckh t ckh t cks t cks t ckh cs ras cas we cke t cms t cmh t cms t cmh t cms t cmh t cms t cmh t as t ah t ck www.datasheet.co.kr datasheet pdf - http://www..net/
W9812G2IB publication release date: mar. 09, 2010 - 19 - revision a04 10.2 read timing read cas latency t ac t lz t ac t oh t hz t oh burst length read command clk cs ras cas we a0-a11 bs0,1 dq valid data-out valid data-out www.datasheet.co.kr datasheet pdf - http://www..net/
W9812G2IB publication release date: mar. 09, 2010 - 20 - revision a04 10.3 control timing of input/output data t cmh t cms t cmh t cms t ds t dh t ds t dh t ds t dh t ds t dh valid data-out valid data-out valid data-out valid data-in valid data-in valid data-in valid data-in t ckh t cks t ckh t cks t ds t dh t ds t dh t dh t ds t ds t dh valid data-in valid data-in valid data-in valid data-in t cmh t cms t cmh t cms t oh t ac t oh t ac t oh t hz open t lz t ac t oh t ac t ckh t cks t ckh t cks t oh t ac t oh t ac t oh t ac t oh t ac valid data-out valid data-out valid data-out clk dqm dq0~31 (word mask) (clock mask) clk cke dq0~31 clk control timing of input data control timing of output data (output enable) (clock mask) dqm dq0~31 cke clk dq0~31 www.datasheet.co.kr datasheet pdf - http://www..net/
W9812G2IB publication release date: mar. 09, 2010 - 21 - revision a04 10.4 mode register set cycle a0 a3 addressing mode 0 sequential 1 interleave a0 a9 single write mode 0 burst read and burst write 1 burst read and single write a0 a2 a1 a0 a0 0 0 0 a0 0 0 1 a0 0 1 0 a0 0 1 1 a0 1 0 0 a0 1 0 1 a0 1 1 0 a0 1 1 1 burst length sequential interleave 1 1 2 2 4 4 8 8 reserved reserved full page cas latency reserved reserved 2 3 reserved a0 a6 a5 a4 a0 0 0 0 a0 0 1 0 a0 0 1 1 a0 1 0 0 a0 0 0 1 * "reserved" should stay "0" during mrs cycle. t rsc t cms t cmh t cms t cmh t cms t cmh t cms t cmh t as t ah clk cs ras cas we a0-a11 bs0,1 register set data next command a0 a1 a2 a3 a4 a5 a6 burst length addressing mode cas latency (test mode) a8 a0 a7 a9 a0 write mode a10 bs0 a0 a11 "0" "0" "0" "0" "0" reserved bs1 "0" reserved www.datasheet.co.kr datasheet pdf - http://www..net/
W9812G2IB publication release date: mar. 09, 2010 - 22 - revision a04 11. operating timing example 11.1 interleaved bank read (burst length = 4, cas latency = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 clk dq cke dqm a0-a9, a11 a10 we cs t rc t rc t rc t rc t ras t rp t ras t rp t rp t ras t ras t rcd t rcd t rcd t rcd t ac t ac t ac t ac t rrd t rrd t rrd t rrd active read active read active active active read read precharge precharge precharge raa rbb rac rbd rae raa caw rbb cbx rac cay rbd cbz rae aw0 aw1 aw2 aw3 bx0 bx1 bx2 bx3 cy0 cy1 cy2 cy3 ras cas bs1 bs0 bank #0 idle bank #1 bank #2 bank #3 www.datasheet.co.kr datasheet pdf - http://www..net/
W9812G2IB publication release date: mar. 09, 2010 - 23 - revision a04 11.2 interleaved bank read (burst length = 4, cas latency = 3, auto-precharge) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 clk cke dqm a0-a9, a11 a10 bs1 we cas ras cs bs0 t rc t rc t rc t ras t rp t ras t rp t ras t rp t rcd t rcd t rcd t ac t ac t ac t ac t rrd t rrd t rrd t rrd active read active read active active active read read t rc raa rac rbd rae dq aw0 aw1 aw2 aw3 bx0 bx1 bx2 bx3 cy0 cy1 cy2 cy3 dz0 * ap is the internal precharge start timing ap* ap* raa caw rbb cbx rac cay rbd rae cbz rbb ap* t rcd bank #0 idle bank #1 bank #2 bank #3 www.datasheet.co.kr datasheet pdf - http://www..net/
W9812G2IB publication release date: mar. 09, 2010 - 24 - revision a04 11.3 interleaved bank read (burst length = 8, cas latency = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 t rc t ras t rp t rp t ras t rcd t rcd t rcd t rrd t rrd raa raa cax rbb rbb cby rac rac caz ax0 ax1 ax2 ax3 ax4 ax5 ax6 by0 by1 by4 by5 by6 by7 cz0 clk dq cke dqm a0-a9, a11 a10 bs1 we cas ras cs active read precharge active read precharge active t ac t ac read precharge t ac bs0 bank #0 idle bank #1 bank #2 bank #3 www.datasheet.co.kr datasheet pdf - http://www..net/
W9812G2IB publication release date: mar. 09, 2010 - 25 - revision a04 11.4 interleaved bank read (burst length = 8, cas latency = 3, auto-precharge) a0-a9, a11 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 t rc t ras t rp t ras t rcd t rcd t rcd t rrd t rrd ax0 ax1 ax2 ax3 ax4 ax5 ax6 ax7 by0 by1 by4 by5 by6 cz0 raa raa cax rbb rbb cby rac rac caz * ap is the internal precharge start timing active read active active read t ac t ac t ac clk dq cke dqm a10 we cas ras cs read ap* ap* bs1 bs0 t ras t rp bank #0 idle bank #1 bank #2 bank #3 www.datasheet.co.kr datasheet pdf - http://www..net/
W9812G2IB publication release date: mar. 09, 2010 - 26 - revision a04 11.5 interleaved bank write (burst length = 8) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 t rc t ras t rp t ras t rcd t rcd t rcd t rrd t rrd raa raa cax rbb rbb cby rac rac caz ax0 ax1 by4 by5 by6 by7 cz0 cz1 cz2 write precharge active active write precharge active write clk dq cke dqm a0-a9, a11 a10 bs1 we cas ras cs idle bank #0 bank #1 bank #2 bank #3 bs0 ax4 ax5 ax6 ax7 by0 by1 by2 by3 www.datasheet.co.kr datasheet pdf - http://www..net/
W9812G2IB publication release date: mar. 09, 2010 - 27 - revision a04 11.6 interleaved bank write (burst length = 8, auto-precharge) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 t rc t ras t rp t ras t rcd t rcd t rcd t rrd t rrd raa raa cax rbb rbb cby rab rac ax0 ax1 ax4 ax5 ax6 ax7 by0 by1 by2 by3 by4 by5 by6 by7 cz0 cz1 cz2 caz * ap is the internal precharge start timing clk dq cke dqm a0-a9, a11 a10 bs1 we cas ras cs active write write active bank #0 idle bank #1 bank #2 bank #3 ap* active write ap* bs0 www.datasheet.co.kr datasheet pdf - http://www..net/
W9812G2IB publication release date: mar. 09, 2010 - 28 - revision a04 11.7 page mode read (burst length = 4, cas latency = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 t ccd t ccd t ccd t ras t ras t rcd t rcd t rrd raa raa cai rbb rbb cbx cay cam cbz a0 a1 a2 a3 bx0 bx1 ay0 ay1 ay2 am0 am1 am2 bz0 bz1 bz2 bz3 * ap is the internal precharge start timing clk dq cke dqm a0-a9, a11 a10 bs1 we cas ras cs active read active read read read read precharge t ac t ac t ac t ac t ac bank #0 idle bank #1 bank #2 bank #3 ap* bs0 www.datasheet.co.kr datasheet pdf - http://www..net/
W9812G2IB publication release date: mar. 09, 2010 - 29 - revision a04 11.8 page mode read / write (burst length = 8, cas latency = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 t ras t rcd t wr raa raa cax cay ax0 ax1 ax2 ax3 ax4 ax5 ay1 ay0 ay2 ay4 ay3 qq q q q q dd d d d clk dq cke dqm a0-a9, a11 a10 bs1 we cas ras cs active read write precharge t ac bank #0 idle bank #1 bank #2 bank #3 bs0 www.datasheet.co.kr datasheet pdf - http://www..net/
W9812G2IB publication release date: mar. 09, 2010 - 30 - revision a04 11.9 auto-precharge read (burst length = 4, cas latency = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 clk dq cke dqm a0-a9, a11 a10 we cas ras cs bs1 t rc t ras t rp t ras t rcd t rcd t ac t ac active read ap* active read ap* raa rab raa caw rab cax aw0 aw1 aw2 aw3 * ap is the internal precharge start timing bank #0 idle bank #1 bank #2 bank #3 bs0 bx0 bx2 bx1 bx3 www.datasheet.co.kr datasheet pdf - http://www..net/
W9812G2IB publication release date: mar. 09, 2010 - 31 - revision a04 11.10 auto-precharge write (burst length = 4) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 clk dq cke dqm a0-a9, a11 a10 we cas ras cs bs1 t rc t rc t rp t ras t rp raa t rcd t rcd rab rac raa rab cax rac bx0 bx1 bx2 bx3 active active write ap* active write ap* * ap is the internal precharge start timing bank #0 idle bank #1 bank #2 bank #3 t ras bs0 caw aw0 aw1 aw2 aw3 www.datasheet.co.kr datasheet pdf - http://www..net/
W9812G2IB publication release date: mar. 09, 2010 - 32 - revision a04 11.11 auto refresh cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 all banks prechage auto refresh auto refresh (arbitrary cycle) t rc t rp t rc clk dq cke dqm a0-a9, a11 a10 we cas ras cs bs0,1 www.datasheet.co.kr datasheet pdf - http://www..net/
W9812G2IB publication release date: mar. 09, 2010 - 33 - revision a04 11.12 self refresh cycle clk dq cke dqm a0-a9, a11 a10 bs0,1 we cas ras cs t cks t sb t cks all banks precharge self refresh entry arbitrary cycle t rp self refresh cycle t xsr no operation / command inhibit self refresh exit www.datasheet.co.kr datasheet pdf - http://www..net/
W9812G2IB publication release date: mar. 09, 2010 - 34 - revision a04 11.13 burst read and single write (burst length = 4, cas latency = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 clk cs ras cas we bs1 bs0 a10 a0-a9, a11 dqm cke dq t rcd rba rba cbv cbw cbx cby cbz av0 av1 av2 av3 aw0 ax0 ay0 az0 az1 az2 az3 qq q q d d dqqqq t ac t ac read read single write active bank #0 idle bank #1 bank #2 bank #3 www.datasheet.co.kr datasheet pdf - http://www..net/
W9812G2IB publication release date: mar. 09, 2010 - 35 - revision a04 11.14 power down mode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 raa caa raa cax raa raa ax0 ax1 ax2 ax3 t sb t cks t cks t cks t sb t cks active standby power down mode precharge standby power down mode active nop precharge nop active note: the power down mode is entered by asserting cke "low". all input/output buffers (except cke buffers) are turned off in the power down mode. when cke goes high, command input must be no operation at next clk rising edge. violating refresh requirements during power-down may result in a loss of data. clk dq cke dqm a0-a9, a11 a10 bs we cas ras cs read www.datasheet.co.kr datasheet pdf - http://www..net/
W9812G2IB publication release date: mar. 09, 2010 - 36 - revision a04 11.15 auto-precharge timing (read cycle) read ap 0 11 10 9 8 7 6 5 4 3 2 1 q0 q0 read ap act q1 read ap act q1 q2 ap act read act q0 q3 (1) cas latency=2 read act ap when the auto precharge command is asserted, the period from bank activate command to the start of internal precgarging must be at least t ras (min). represents the read with auto precharge command. represents the start of internal precharging. represents the bank activate command. note: t rp t rp t rp ( a ) burst length = 1 command ( b ) burst length = 2 command ( c ) burst length = 4 command ( d ) burst length = 8 command dq dq dq dq q0 q1 q2 q3 q4 q5 q6 q7 t rp q0 read ap act q0 read ap act q1 q0 read ap act q1 q2 q3 read ap act q0 q1 q2 q3 q4 q5 q6 q7 (2) cas latency=3 t rp t rp t rp t rp ( a ) burst length = 1 command ( b ) burst length = 2 command ( c ) burst length = 4 command ( d ) burst length = 8 command dq dq dq dq www.datasheet.co.kr datasheet pdf - http://www..net/
W9812G2IB publication release date: mar. 09, 2010 - 37 - revision a04 11.16 auto-precharge timing (write cycle) act 01 3 2 (1) cas latency = 2 (a) burst length = 1 dq 45 7 68911 10 write d0 act ap command (b) burst length = 2 dq write d0 act ap command trp trp d1 (c) burst length = 4 dq write d0 act ap command trp d1 (d) burst length = 8 dq write d0 act ap command trp d1 d2 d3 d2 d3 d4 d5 d6 d7 (2) cas latency = 3 (a) burst length = 1 dq write d0 act ap command (b) burst length = 2 dq write d0 act ap command trp trp d1 (c) burst length = 4 dq write d0 act ap command trp d1 (d) burst length = 8 dq write d0 ap command trp d1 d2 d3 d2 d3 d4 d5 d6 d7 twr twr twr twr twr twr twr twr 12 act represents the write with auto precharge command. represents the start of internal precharing. represents the bank active command. write ap act act when the /auto precharge command is asserted,the period from bank activate command to the start of intermal precgarging must be at least tras (min). note ) clk www.datasheet.co.kr datasheet pdf - http://www..net/
W9812G2IB publication release date: mar. 09, 2010 - 38 - revision a04 11.17 timing chart of read to write cycle note: the output data must be masked by dqm to avoid i/o conflict 11 10 9 8 7 6 5 4 3 2 1 0 (1) cas latency=2 in the case of burst length = 4 read read write write dq dq ( b ) command dqm dqm d0 d1 d2 d3 d0 d1 d2 d3 ( a ) command (2) cas latency=3 read write read write d0 d1 d2 d3 ( a ) command dq dq dqm ( b ) command dqm d0 d1 d2 d3 11.18 timing chart of write to read cycle read write 0 11 10 9 8 7 6 5 4 3 2 1 q0 read q1 q2 q3 read read write write q0 q1 q2 q3 write q0 q1 q2 q3 d0 d1 dq dq ( a ) command dq dq dqm ( b ) command dqm ( a ) command ( b ) command dqm dqm in the case of burst length=4 (1) cas latency=2 (2) cas latency=3 d0 d0 d1 q0 q1 q2 q3 d0 www.datasheet.co.kr datasheet pdf - http://www..net/
W9812G2IB publication release date: mar. 09, 2010 - 39 - revision a04 11.19 timing chart of burst st op cycle (burst stop command) read bst 0 11 10 9 8 7 6 5 4 3 2 1 dq q0 q1 q2 q3 bst ( a ) cas latency =2 command ( b )cas latency = 3 (1) read cycle q4 (2) write cycle command read command q0 q1 q2 q3 q4 q0 q1 q2 q3 q4 dq dq write bst note: represents the burst stop command bst 11.20 timing chart of burst stop cycle (precharge command) 01 11 10 9 8 7 6 5 4 3 2 (1) read cycle (a) c a s latency =2 c om m and q0 q1 q2 q3 q4 prcg read (b) c a s latency =3 c om m and q0 q1 q2 q3 q4 prcg read dq dq (2) w rite cycle command q0 q1 q2 q3 q4 prcg write dq dqm tw r www.datasheet.co.kr datasheet pdf - http://www..net/
W9812G2IB publication release date: mar. 09, 2010 - 40 - revision a04 11.21 cke/dqm input timing (write cycle) 7 6 5 4 3 2 1 cke mask ( 1 ) d1 d6 d5 d3 d2 clk cycle no. external internal cke dqm dq 7 6 5 4 3 2 1 ( 2 ) d1 d6 d5 d3 d2 clk cycle no. external internal cke dqm dq 7 6 5 4 3 2 1 ( 3 ) d1 d6 d5 d4 d3 d2 clk cycle no. external cke dqm dq dqm mask dqm mask cke mask cke mask internal clk clk clk www.datasheet.co.kr datasheet pdf - http://www..net/
W9812G2IB publication release date: mar. 09, 2010 - 41 - revision a04 11.22 cke/dqm input timing (read cycle) 7 6 5 4 3 2 1 ( 1 ) q1 q6 q4 q3 q2 clk cycle no. external internal cke dqm dq open open 7 6 5 4 3 2 1 q1 q6 q3 q2 clk cycle no. external internal cke dqm dq open ( 2 ) 7 6 5 4 3 2 1 q1 q6 q2 clk cycle no. external internal cke dqm dq q5 q4 ( 3 ) q4 clk clk clk q3 www.datasheet.co.kr datasheet pdf - http://www..net/
W9812G2IB publication release date: mar. 09, 2010 - 42 - revision a04 12. package specification 12.1 tfbga 90 balls (8x13 mm 2 , ball pitch: 0.8mm, ?=0.45mm) d d2 e e 2 e e www.datasheet.co.kr datasheet pdf - http://www..net/
W9812G2IB publication release date: mar. 09, 2010 - 43 - revision a04 13. revision history version date page description a01 nov. 06, 2008 all initial formal data sheet a02 jan. 15, 2009 3, 14~16 change power supply voltage supports from 3.0v~3.6v to 2.7v~3.6v a03 sep. 29, 2009 14 revise input/output voltage and power supply voltage spec. in section 9.1 absolute maximum ratings table a04 mar. 09, 2010 3, 14~16 added -6a automotive grade parts important notice winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surg ical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. further more, winbond products are not intended for applications wherein failure of winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify winbond for any damages resulting from such improper use or sales. www.datasheet.co.kr datasheet pdf - http://www..net/

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